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Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs.

, , and . ACM Trans. Archit. Code Optim., 12 (2): 25:1-25:24 (2015)

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A Power Model for Register-Sharing Structures., and . DIPES, volume 271 of IFIP, page 131-142. Springer, (2008)Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors., , and . HiPC, volume 2228 of Lecture Notes in Computer Science, page 192-203. Springer, (2001)Qwerty: A Basis-Oriented Quantum Programming Language., , , and . CoRR, (2024)High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm., and . IEEE Trans. Parallel Distributed Syst., 16 (12): 1132-1142 (2005)Iterative Modulo Scheduling., , , and . IEEE Micro, 38 (1): 115-117 (2018)System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 129-137 (2000)A Fast Interrupt Handling Scheme for VLIW Processors., , , , , and . IEEE PACT, page 136-141. IEEE Computer Society, (1998)Path Prediction for High Issue-Rate Processors., , and . IEEE PACT, page 178-188. IEEE Computer Society, (1997)Using branch handling hardware to support profile-driven optimization., , and . MICRO, page 12-21. ACM / IEEE Computer Society, (1994)Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors., and . MICRO, page 82-92. ACM/IEEE Computer Society, (1999)