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Disambiguation of "Tsukamoto, Sanroku"

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32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.

, , , , , , , , , , and . ISSCC, page 36-37. IEEE, (2013)

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Masaji Tsukamoto

Masaaki Tsukamoto

Nobuko Ohashi Tsukamoto

 

Other publications of authors with the same name

A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration., , , and . IEEE Trans. Biomed. Circuits Syst., 4 (6): 410-416 (2010)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , and . CICC, page 495-498. IEEE, (2008)A 6b 3GS/s flash ADC with background calibration., , , and . CICC, page 283-286. IEEE, (2009)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine., , , , , , , , , and 1 other author(s). CISIS, volume 611 of Advances in Intelligent Systems and Computing, page 432-438. Springer, (2017)A 1 GHz CMOS comparator with dynamic offset control technique., , and . ASP-DAC, page 103-104. IEEE, (2009)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , and 2 other author(s). CICC, page 279-282. IEEE, (2009)A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS., , , , and . VLSI-DAT, page 1-4. IEEE, (2012)A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array., , , and . VLSI-DAT, page 1-4. IEEE, (2012)A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing., , , and . ISSCC, page 452-614. IEEE, (2007)