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A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration., , , и . IEEE Trans. Biomed. Circuits Syst., 4 (6): 410-416 (2010)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , и . CICC, стр. 495-498. IEEE, (2008)A 6b 3GS/s flash ADC with background calibration., , , и . CICC, стр. 283-286. IEEE, (2009)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 36-37. IEEE, (2013)A 1 GHz CMOS comparator with dynamic offset control technique., , и . ASP-DAC, стр. 103-104. IEEE, (2009)Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine., , , , , , , , , и 1 other автор(ы). CISIS, том 611 из Advances in Intelligent Systems and Computing, стр. 432-438. Springer, (2017)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , и 2 other автор(ы). CICC, стр. 279-282. IEEE, (2009)A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing., , , и . ISSCC, стр. 452-614. IEEE, (2007)A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration., , , и . ISSCC, стр. 384-385. IEEE, (2010)A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2012)