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Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning., , and . DAC, page 59:1-59:6. ACM, (2016)3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (12): 2005-2009 (2014)CRAFT: Criticality-Aware Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks., , , and . CoRR, (2023)Low-power shared memory architecture power mode for mobile system-on-chip., , , , and . IEICE Electron. Express, (2014)Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks., , , and . DAC, page 1075-1080. IEEE, (2021)Devil in a box: Installing backdoors in electronic door locks., , , and . PST, page 139-144. IEEE Computer Society, (2015)Factored Radix-8 Systolic Array for Tensor Processing., , , and . DAC, page 1-6. IEEE, (2020)DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault Analysis., and . DAC, page 129. ACM, (2019)MRLoc: Mitigating Row-hammering based on memory Locality., and . DAC, page 19. ACM, (2019)Test cost reduction for X-value elimination by scan slice correlation analysis., and . DAC, page 78:1-78:6. ACM, (2018)