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A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor.

, and . APCCAS, page 1931-1934. IEEE, (2006)

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A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications., and . ACM Great Lakes Symposium on VLSI, page 101-106. ACM, (2000)An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (4): 776-788 (2021)An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications., , , , , and . ISCAS, page 1370-1373. IEEE, (2015)Low quiescent current variable output digital controlled voltage regulator., and . ISCAS, page 609-612. IEEE, (2010)A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM., , and . ISCAS, IEEE, (2006)A fully-differential subthreshold SRAM cell with auto-compensation., and . APCCAS, page 1771-1774. IEEE, (2008)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2015)Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory., , and . APCCAS, page 1301-1304. IEEE, (2006)Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application., , , , and . SoCC, page 18-23. IEEE, (2016)Low temperature (<180 °C) bonding for 3D integration., , , , , , , , , and 1 other author(s). 3DIC, page 1-5. IEEE, (2013)