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An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks.

, , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (4): 776-788 (2021)

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A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM., , and . ISCAS, IEEE, (2006)Low quiescent current variable output digital controlled voltage regulator., and . ISCAS, page 609-612. IEEE, (2010)Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application., , , , and . SoCC, page 18-23. IEEE, (2016)Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory., , and . APCCAS, page 1301-1304. IEEE, (2006)A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications., and . ACM Great Lakes Symposium on VLSI, page 101-106. ACM, (2000)Power noise suppression technique using active decoupling capacitor for TSV 3D integration., , and . SoCC, page 209-212. IEEE, (2010)On-demand memory sub-system for multi-core SoCs., , and . SoCC, page 122-127. IEEE, (2011)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions., , , and . SoCC, page 19-23. IEEE, (2011)A fully-differential subthreshold SRAM cell with auto-compensation., and . APCCAS, page 1771-1774. IEEE, (2008)