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MDCT IP Core Generator with Architectural Model Simulation., , , and . VLSI-SoC, page 18-23. IEEE, (2006)Natural logarithm and division floating-point high throughput co-processor implemented in FPGA.. NORCAS, page 1-6. IEEE, (2016)High Throughput Floating Point Exponential Function Implemented in FPGA.. ISVLSI, page 97-100. IEEE Computer Society, (2015)FPGA Implementation of a Fast MDCT Algorithm., , , and . DDECS, page 228-229. IEEE Computer Society, (2006)Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults., and . Integr., (2018)High Throughput Floating-Point Dividers Implemented in FPGA.. DDECS, page 291-294. IEEE Computer Society, (2015)StarCraft strategy classification of a large human versus human game replay dataset., , and . FedCSIS, volume 25 of Annals of Computer Science and Information Systems, page 137-140. (2021)Instance Segmentation Model Created from Three Semantic Segmentations of Mask, Boundary and Centroid Pixels Verified on GlaS Dataset., , and . FedCSIS, volume 21 of Annals of Computer Science and Information Systems, page 569-576. (2020)An Improved MDCT IP Core Generator with Architectural Model Simulation., , , and . DDECS, page 193-198. IEEE Computer Society, (2007)MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio., , , , and . DDECS, page 144-147. IEEE Computer Society, (2009)