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Другие публикации лиц с тем же именем

Not All Ops Are Created Equal!, , и . CoRR, (2018)Modeling SRAM dynamic VMIN., , , и . ICICDT, стр. 1-4. IEEE, (2014)Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs., , , , и . ISLPED, стр. 145-150. IEEE/ACM, (2011)A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM., , , и . ISLPED, стр. 307-310. ACM, (2014)Impact of voltage scaling on nanoscale SRAM reliability., и . DATE, стр. 387-392. IEEE, (2009)Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN., , , и . DATE, стр. 1819-1824. EDA Consortium San Jose, CA, USA / ACM DL, (2013)TIMBER: Time borrowing and error relaying for online timing error resilience., , , и . DATE, стр. 1554-1559. IEEE Computer Society, (2010)A black box method for stability analysis of arbitrary SRAM cell structures., , , , , , и . DATE, стр. 795-800. IEEE Computer Society, (2010)Analytical model for TDDB-based performance degradation in combinational logic., , , и . DATE, стр. 423-428. IEEE Computer Society, (2010)AttentiveNAS: Improving Neural Architecture Search via Attentive Sampling., , , и . CoRR, (2020)