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Disambiguation of "Desai, Shaishav"

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A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop.

, , , , , , , , , , , , , , , , and . CICC, page 1-4. IEEE, (2014)

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Rumana Desai-Hahn

Natvarlal Desai

Vasant Desai

Renate Desai

Shashikant Desai

 

Other publications of authors with the same name

A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process., , and . ISSCC, page 308-605. IEEE, (2007)A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes., , and . CICC, page 239-242. IEEE, (2009)6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET., , , , , , , , , and 4 other author(s). ISSCC, page 120-122. IEEE, (2020)A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency., , , , , , , , , and 29 other author(s). ESSCIRC, page 458-461. IEEE, (2012)An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications., , and . MWSCAS, page 1-4. IEEE, (2022)A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications., , , , , , , , , and 7 other author(s). MWSCAS, page 5-8. IEEE, (2012)A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2014)A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems., , , , , , , , , and 18 other author(s). ISSCC, page 104-105. IEEE, (2007)A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC., , and . ISCAS, page 1-5. IEEE, (2024)