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Disambiguation of "Yamaguchi, Hisakatsu"

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A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.

, , , , , , , , , , , , , , and . ISSCC, page 168-169. IEEE, (2010)

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Shigeo Yamaguchi

Fabian Yamaguchi

Ichiro Yamaguchi

Ichiro Yamaguchi

Yoko Yamaguchi

 

Other publications of authors with the same name

Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management., , , and . DATE, page 1536-1541. IEEE, (2021)F6: Energy-efficient I/O design for next-generation systems., , , , , and . ISSCC, page 520-521. IEEE, (2014)A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS., , , , , , and . ISSCC, page 166-167. IEEE, (2010)On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR., , , and . IEEE J. Solid State Circuits, 53 (3): 750-761 (2018)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution., , , , , , , , , and 6 other author(s). VLSIC, page 1-2. IEEE, (2014)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)F3: Emerging technologies for wireline communication., , , , , , and . ISSCC, page 504-505. IEEE, (2013)6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS., , , , , , and . ISSCC, page 120-121. IEEE, (2017)6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance., , , , and . ISSCC, page 122-123. IEEE, (2017)