Author of the publication

Contention and energy aware mapping for real-time applications on Network-on-Chip.

, , , and . ISOCC, page 72-76. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Multi-Label Classification of Fundus Images With EfficientNet., , , , and . IEEE Access, (2020)A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (10): 3787-3791 (October 2023)A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications., , , and . ISCAS, page 1-4. IEEE, (2017)An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits., , , and . ICCAD, page 1-9. IEEE, (2021)TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations., , , , , , , and . ICCAD, page 1-9. IEEE, (2023)An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations., , , , , and . ISCAS, page 1-5. IEEE, (2023)High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory., , , and . ISCAS, page 1-4. IEEE, (2021)An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits., , , and . ISCAS, page 1-5. IEEE, (2021)Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory., , , , , , and . FPT, page 233-236. IEEE, (2016)A Ternary Memristive Logic-in-Memory Design for Fast Data Scan., , , , , , and . ICTA, page 183-184. IEEE, (2021)