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Bias Temperature Instability analysis of FinFET based SRAM cells., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Electrical Modeling of STT-MRAM Defects., , , , and . ITC, page 1-10. IEEE, (2018)Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach., , and . Asian Test Symposium, page 434-439. IEEE Computer Society, (2005)Evaluation of Intra-Word Faults in Word-Oriented RAMs., , and . Asian Test Symposium, page 283-288. IEEE Computer Society, (2004)Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories., and . DATE, page 265-268. IEEE, (2011)Manifestation of Precharge Faults in High Speed DRAM Devices., , and . DDECS, page 179-184. IEEE Computer Society, (2007)Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests., , and . ITC, page 114-123. IEEE Computer Society, (2004)Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories., and . Asian Test Symposium, page 340-347. IEEE Computer Society, (1998)Untestable faults identification in GPGPUs for safety-critical applications., , , , and . ICECS, page 570-573. IEEE, (2019)S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX., , , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 295-307. Springer, (2020)