( en | de | ru )

 

Disambiguation of "Krishnamurthy, Ram K."

Author of the publication

copydeleteadd this publication to your clipboard
Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends.

, , , , , and . IEEE J. Solid State Circuits, 36 (11): 1636-1646 (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mahalakshmi Krishnamurthy

Adarsh Krishnamurthy

Arvind Krishnamurthy

Johann Ram

Ram Gopal

 

Other publications of authors with the same name

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming., , , , , , , , and . ESSCIRC, page 437-440. IEEE, (2023)16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2014)A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS., , , , and . VLSI Circuits, page 255-256. IEEE, (2018)Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference., , , and . IEEE J. Solid State Circuits, 41 (1): 3-6 (2006)An Inductor-First Single-Inductor Multiple-Output Hybrid DC-DC Converter With Integrated Flying Capacitor for SoC Applications., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 4823-4836 (2022)25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range., , , , , , , , , and 4 other author(s). ISSCC, page 396-398. IEEE, (2020)A CMOS wave-pipelined image processor for real-time morphology ., and . ICCD, page 638-643. IEEE Computer Society, (1995)microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware., , , , , and . ESSCIRC, page 421-424. IEEE, (2023)A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS., , , , and . ESSCIRC, page 316-319. IEEE, (2007)