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A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications., , , , , , and . ASICON, page 1-4. IEEE, (2015)Employing the mixed FBB/RBB in the design of FinFET logic gates., , , , , , and . ASICON, page 1-4. IEEE, (2015)FPGA Implementation of Quantized Convolutional Neural Networks., , , , , and . ICCT, page 1605-1610. IEEE, (2019)Polymorphic gate based IC watermarking techniques., , , , , , and . ASP-DAC, page 90-96. IEEE, (2018)A Discrete STFT Processor for Real-time Spectrum Analysis., , and . APCCAS, page 1943-1946. IEEE, (2006)Ultralow-power high-speed flip-flop based on multimode FinFETs., , , , , and . Sci. China Inf. Sci., 59 (4): 042404:1-042404:11 (2016)A 3D Convolutional Neural Network for Emotion Recognition based on EEG Signals., , , , and . IJCNN, page 1-6. IEEE, (2020)A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs., , and . APCCAS, page 9-12. IEEE, (2006)A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs., , , , , , , and . ISCAS, page 129-132. IEEE, (2013)Design of Low-Power High-Performance FinFET Standard Cells., , , , , and . CSSP, 37 (5): 1789-1806 (2018)