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Disambiguation of "Dasgupta, Sudeb"

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Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.

, , , , and . VLSI Design, page 183-188. IEEE Computer Society, (2007)

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Shivaji Dasgupta

Shyamal Dasgupta

Subho Dasgupta

Subhoranjan Dasgupta

Shyamal Dasgupta

 

Other publications of authors with the same name

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (8): 2657-2663 (2023)Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm., , , and . ICM, page 166-169. IEEE, (2021)Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization., , , , , and . ISQED, page 251-256. IEEE, (2021)Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design., , , , and . VLSI Design, page 183-188. IEEE Computer Society, (2007)A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz., , and . ISVLSI, page 108-113. IEEE Computer Society, (2011)An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime., , , , , , and . APCCAS, page 105-109. IEEE, (2023)SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology., , , , , and . ISQED, page 1-8. IEEE, (2024)An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN., , , and . AICAS, page 184-188. IEEE, (2024)Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application., , , and . ISCAS, page 1-5. IEEE, (2024)Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance., , and . ISQED, page 717-722. IEEE, (2012)