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A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.

D. Jiang, L. Qi, S. Sin, F. Maloberti, and R. Martins. IEEE J. Solid State Circuits, 56 (8): 2375-2387 (2021)

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Sai Li

Sai Zhang

Sai Qian

Sin Wong

Other publications of authors with the same name

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.H. Wei, C. Chan, U. Chio, S. Sin, S. U., R. Martins, and F. Maloberti. IEEE J. Solid State Circuits, 47 (11): 2763-2772 (2012)An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters.Y. Wu, W. Choi, C. Lam, M. Wong, S. Sin, and R. Martins. IEEE Trans. Circuits Syst. II Express Briefs, 69 (10): 4133-4137 (2022)Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters.D. Feng, F. Maloberti, S. Sin, and R. Martins. IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (4): 537-547 (2015)A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.Y. Jiang, K. Wong, C. Cai, S. Sin, S. U, and R. Martins. APCCAS, page 1011-1014. IEEE, (2010)A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.H. Wei, U. Chio, Y. Zhu, S. Sin, S. U, and R. da Silva Martins. APCCAS, page 1192-1195. IEEE, (2008)A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC.K. Li, S. Sin, L. Qi, W. Zhao, G. Wang, and R. Martins. ISCAS, page 551-555. IEEE, (2022)A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators.Y. Jiang, K. Wong, C. Cai, S. Sin, S. U., and R. Martins. ICECS, page 547-550. IEEE, (2010)An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications.G. Yin, U. Chio, H. Wei, S. Sin, S. U., R. Martins, and Z. Wang. ICECS, page 878-881. IEEE, (2010)Hybrid loopfilter sigma-delta modulator with NTF zero compensation.A. Hussain, S. Sin, S. U, and R. Martins. ISOCC, page 76-79. IEEE, (2011)A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction.J. Zhong, Y. Zhu, C. Chan, S. Sin, S. U, and R. Martins. ESSCIRC, page 169-172. IEEE, (2016)

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Disambiguation of "Sin, Sai-Weng"

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A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.

Please choose a person to relate this publication to

Sai Li

Sai Zhang

Sai Zhang

Sai Qian

Sin Wong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sin, Sai-Weng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.

Please choose a person to relate this publication to

Sai Li

Sai Zhang

Sai Zhang

Sai Qian

Sin Wong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.