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Co-design of deep neural nets and neural net accelerators for embedded vision applications., , , , , and . DAC, page 148:1-148:6. ACM, (2018)FireMarshal: Making HW/SW Co-Design Reproducible and Reliable., and . ISPASS, page 299-309. IEEE, (2021)A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET., , , , , , , , , and 9 other author(s). ESSCIRC, page 259-262. IEEE, (2021)FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud., , , , , , , , , and 6 other author(s). ISCA, page 29-42. IEEE Computer Society, (2018)Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs., , , , and . ISCAS, page 1-5. IEEE, (2021)Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs., , , , , , , , , and 7 other author(s). IEEE Micro, 40 (4): 10-21 (2020)Invited: Chipyard - An Integrated SoC Research and Implementation Environment., , , , , , , , , and 8 other author(s). DAC, page 1-6. IEEE, (2020)Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration., , , , , , , , , and 9 other author(s). DAC, page 769-774. IEEE, (2021)FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design., , , , , , and . ASPLOS, page 715-731. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors., , , , and . ISPASS, page 310-320. IEEE, (2021)