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A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links.

, , , , , and . ISCAS, page 1-5. IEEE, (2023)

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A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links., , , , , and . ISCAS, page 1-5. IEEE, (2023)On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs., , , , and . VLSIC, page 1-2. IEEE, (2014)On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs., , , , and . IEEE J. Solid State Circuits, 50 (4): 845-855 (2015)High speed ADCs for wireline applications., , , and . MWSCAS, page 579-582. IEEE, (2017)A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE., , , , and . CICC, page 1-4. IEEE, (2014)An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection., , , , and . CICC, page 1-8. IEEE, (2013)A hybrid phase-locked loop for CDR Applications., , and . ISCAS, page 2533-2536. IEEE, (2011)An RF power harvesting system with input-tuning for long-range RFID tags., , and . ISCAS, page 4085-4088. IEEE, (2010)A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support., , , , , , , , , and 1 other author(s). ISSCC, page 106-108. IEEE, (2018)