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Post-silicon patching for verification/debugging with high-level models and programmable logic.

, and . ASP-DAC, page 232-237. IEEE, (2012)

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Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse., , and . IRI, page 318-325. IEEE Systems, Man, and Cybernetics Society, (2005)Tutorial: "Post silicon debug of SOC designs"., and . SoCC, page 18. IEEE, (2011)A small biped entertainment robot exploring attractive applications., , , , and . ICRA, page 471-476. IEEE, (2003)234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes., , and . HPCS, page 421-428. IEEE, (2015)On variable ordering of binary decision diagrams for the application of multi-level logic synthesis., , and . EURO-DAC, page 50-54. EEE Computer Society, (1991)Global transaction ordering in Network-on-Chips for post-silicon validation., and . ISQED, page 284-289. IEEE, (2011)Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition., , , and . IEEE Trans. Computers, 64 (6): 1579-1593 (2015)Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog., , , and . ICLP, volume 225 of Lecture Notes in Computer Science, page 695-709. Springer, (1986)Program Slicing of Hardware Description Languages., , , , , and . CHARME, volume 1703 of Lecture Notes in Computer Science, page 298-312. Springer, (1999)An Image-Based CAPTCHA Using Sophisticated Mental Rotation., , , , and . HCI (24), volume 8533 of Lecture Notes in Computer Science, page 57-68. Springer, (2014)