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Warehouse-scale video acceleration: co-design and deployment in the wild., , , , , , , , , and 42 other author(s). ASPLOS, page 600-615. ACM, (2021)Synthesis of Sequential Circuits for Robust Path Delay Fault Testability., and . VLSI Design, page 275-280. IEEE Computer Society, (1993)A structured test re-use methodology for core-based system chips., and . ITC, page 294-302. IEEE Computer Society, (1998)Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches., and . ICCD, page 91-96. IEEE Computer Society, (1994)Low power compression architecture.. VTS, page 183-187. IEEE Computer Society, (2010)Genesis: A Behavioral Synthesis System for Hierarchical Testability., and . EDAC-ETC-EUROASIC, page 272-276. IEEE Computer Society, (1994)Test Compaction by Using Linear-Matrix Driven Scan Chains.. DFT, page 185-190. IEEE Computer Society, (2003)A Unifying Methodology for Intellectual Property and Custom Logic Testing., , and . ITC, page 639-648. IEEE Computer Society, (1996)Optimizing Test Data Volume Using Hybrid Compression., , , , and . ATS, page 157-162. IEEE Computer Society, (2008)A Comparative Analysis and Design Criteria of MAC, SMAC, and TMAC Protocols in Wireless Sensor Network., , , , , and . ICCCNT, page 1-6. IEEE, (2023)