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Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis., , , and . DSD, page 308-315. IEEE Computer Society, (2002)Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis., , , , and . DSD, page 267-273. IEEE Computer Society, (2008)Multispeculative additive trees in high-level synthesis., , , , and . DATE, page 188-193. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Using Speculative Functional Units in high level synthesis., , , , and . DATE, page 1779-1784. IEEE Computer Society, (2010)Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (9): 1589-1601 (2007)Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources., , and . J. Syst. Archit., 49 (12-15): 505-519 (2003)Behavioural Bitwise Scheduling Based on Computational Effort Balancing., , , and . DATE, page 684-685. IEEE Computer Society, (2004)Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis., , , and . DATE, page 1252-1257. IEEE Computer Society, (2005)Area optimization of multi-cycle operators in high-level synthesis., , , and . DATE, page 449-454. EDA Consortium, San Jose, CA, USA, (2007)