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Hardware Acceleration of Hash Operations in Modern Microprocessors., , , and . IEEE Trans. Computers, 70 (9): 1412-1426 (2021)Robust window-based multi-node technology-independent logic minimization., , and . ACM Great Lakes Symposium on VLSI, page 357-362. ACM, (2009)Engineering Change in a Non-Deterministic FSM Setting., , , , , and . DAC, page 451-456. ACM Press, (1996)Boolean satisfiability using noise based logic., , and . DAC, page 1260-1261. ACM, (2012)A fast, analytical estimator for the SEU-induced pulse width in combinational designs., , and . DAC, page 918-923. ACM, (2008)Forbidden transition free crosstalk avoidance CODEC design., , and . DAC, page 986-991. ACM, (2008)A flash-based digital circuit design flow., and . ICCAD, page 6. ACM, (2016)A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells., , and . ICCD, page 433-440. IEEE, (2020)NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform., , , and . ICCD, page 41-48. IEEE, (2021)A design flow to optimize circuit delay by using standard cells and PLAs., , , , , and . ACM Great Lakes Symposium on VLSI, page 217-222. ACM, (2006)