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A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS., , , и . ISSCC, стр. 436-438. IEEE, (2011)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , и 2 other автор(ы). IEICE Trans. Electron., 93-C (3): 295-302 (2010)A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid., , , , , и . ISSCC, стр. 2102-2111. IEEE, (2006)22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS., , , , , , и . ISSCC, стр. 166-167. IEEE, (2010)A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers., , , , , и . CICC, стр. 1-4. IEEE, (2010)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , и 2 other автор(ы). CICC, стр. 279-282. IEEE, (2009)An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS., , , и . IEEE J. Solid State Circuits, 46 (12): 3140-3149 (2011)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , и . CICC, стр. 495-498. IEEE, (2008)A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS., , , , , и . IEEE J. Solid State Circuits, 40 (4): 986-993 (2005)