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A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , и . VLSIC, стр. 1-2. IEEE, (2014)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 64-65. IEEE, (2016)Error-Free Loopback of a Compact 25 Gb/s × 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error Correction., , , , , , , , , и 3 other автор(ы). OFC, стр. 1-3. IEEE, (2018)Ultra-Low-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver., , , , , , , , и . ECOC, стр. 1-3. IEEE, (2017)Non-binary SAR ADC with digital error correction for low power applications., , , , , , , , и . APCCAS, стр. 196-199. IEEE, (2010)Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design., , , , , , и . GECCO (Companion), стр. 405-406. ACM, (2019)A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 86-88. IEEE, (2012)A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects., , , , , , , , , и 14 other автор(ы). OFC, стр. 1-3. IEEE, (2015)SAR ADC Algorithm with Redundancy and Digital Error Correction., , , , , , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (2): 415-423 (2010)A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications., , , , и . ESSCIRC, стр. 349-352. IEEE, (2012)