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Quantifying and coping with parametric variations in 3D-stacked microarchitectures., , , , , and . DAC, page 144-149. ACM, (2010)Cost-effective design of scalable high-performance systems using active and passive interposers., , , and . ICCAD, page 728-735. IEEE, (2017)The impact of 3-dimensional integration on the design of arithmetic units., and . ISCAS, IEEE, (2006)Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources., , , and . MICRO, page 1169-1181. ACM, (2021)Die Stacking (3D) Microarchitecture., , , , , , , , , and 5 other author(s). MICRO, page 469-479. IEEE Computer Society, (2006)A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch., , , , and . MICRO, page 247-257. IEEE Computer Society, (2012)Adaptive Caches: Effective Shaping of Cache Behavior to Workloads., , and . MICRO, page 385-396. IEEE Computer Society, (2006)Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits., , and . DATE, page 142-145. IEEE, (2021)AMD InstinctTM MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture., , , , , und . VLSI Technology and Circuits, Seite 1-2. IEEE, (2023)Circuits for wide-window superscalar processors., , , und . ISCA, Seite 236-247. IEEE Computer Society, (2000)