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Другие публикации лиц с тем же именем

Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems., , и . SLIP, стр. 1-8. IEEE, (2019)Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing., , , , и . AsianHOST, стр. 74-79. IEEE, (2018)Network-on-Chip Design Guidelines for Monolithic 3-D Integration., , и . IEEE Micro, 39 (6): 46-53 (2019)Power Profiling of Modern Die-Stacked Memory., , , , и . IEEE Comput. Archit. Lett., 18 (2): 132-135 (2019)Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges., , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 347-352. ACM, (2016)Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration., , , , и . ICCAD, стр. 56. ACM, (2016)Yield-driven minimum energy CMOS cell design., , , и . ACSCC, стр. 1010-1014. IEEE, (2012)Security Threats and Countermeasures in Three-Dimensional Integrated Circuits., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 321-326. ACM, (2017)Cost-effective design of scalable high-performance systems using active and passive interposers., , , и . ICCAD, стр. 728-735. IEEE, (2017)Thermal-aware 3D design for side-channel information leakage., , , , и . ICCD, стр. 520-527. IEEE Computer Society, (2016)