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Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor., , and . SoCPaR, volume 1182 of Advances in Intelligent Systems and Computing, page 266-276. Springer, (2019)COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores., , , , , , , , , and 1 other author(s). ARCS, volume 13949 of Lecture Notes in Computer Science, page 105-119. Springer, (2023)Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation., , , , , , , and . RAPIDO@HiPEAC, page 35-41. ACM, (2024)Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors., , , , , , , , , and 5 other author(s). DATE, page 136-141. IEEE, (2021)Multilevel simulation-based co-design of next generation HPC microprocessors., , , , , , , , , and 10 other author(s). PMBS, page 18-29. IEEE, (2021)Evolution of application-specific cache mappings., , and . Int. J. Hybrid Intell. Syst., 16 (3): 149-161 (2020)Adversarial classification via distributional robustness with Wasserstein ambiguity., and . Math. Program., 198 (2): 1411-1447 (April 2023)Multimodal Biosensor System for Exhaled Breath Based Lung Cancer Diagnosis., , , , , and . SENSORS, page 1-4. IEEE, (2023)Development of a Reinforcement Learning-Based Adaptive Scheduling Algorithm for Block Assembly Production Line., , , and . WSC, page 1-12. IEEE, (2021)Design of A Power-, Delay-, and Emergency-Efficient Protocol of Ubiquitous Sensor Network Systems for Silver Town Applications., , , , and . FGCN (2), page 306-309. IEEE Computer Society, (2008)978-0-7695-3431-2.