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A BF16 FMA is All You Need for DNN Training., , , , and . ARITH, page 9. IEEE, (2022)Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory., , , , , , and . PACT, page 361-371. IEEE Computer Society, (2011)Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors., , , , , , , , , and 5 other author(s). DATE, page 136-141. IEEE, (2021)Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors., , , , , and . ICMLA, page 49-56. IEEE, (2020)Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training., , , , and . ICMLA, page 980-987. IEEE, (2021)gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator., , and . ICPP, page 29:1-29:11. ACM, (2021)DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations., , , , , , and . ISCA, page 30:1-30:13. ACM, (2023)Multilevel simulation-based co-design of next generation HPC microprocessors., , , , , , , , , and 10 other author(s). PMBS, page 18-29. IEEE, (2021)Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor., , , , and . IEEE ACM Trans. Comput. Biol. Bioinform., 20 (5): 3139-3153 (September 2023)PLANAR: a programmable accelerator for near-memory data rearrangement., , , and . ICS, page 164-176. ACM, (2021)