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Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication.

, , , , and . MICRO, page 285-297. IEEE Computer Society, (2018)

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Design and architecture of the IBM Quantum Engine Compiler., , , , , , , , , and . CoRR, (2024)Profile-Driven Instruction Mapping for Dataflow Architectures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 3017-3025 (2006)3D stacking of high-performance processors., , , , , , , , , and . HPCA, page 500-511. IEEE Computer Society, (2014)A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design., , , and . MICRO, page 3-14. IEEE Computer Society, (2006)CramSim: controller and memory simulator., and . MEMSYS, page 83-85. ACM, (2017)Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling., , , and . ASP-DAC, page 786-791. IEEE Computer Society, (2007)Microarchitectural floorplanning under performance and thermal tradeoff., , , , , , and . DATE, page 1288-1293. European Design and Automation Association, Leuven, Belgium, (2006)Floorplanning challenges in early chip planning., , , , , , and . SoCC, page 388-393. IEEE, (2011)Power management of multi-core chips: Challenges and pitfalls., , , , , , , , , and 1 other author(s). DATE, page 977-982. IEEE, (2012)A unified methodology for power supply noise reduction in modern microarchitecture design., , , and . ASP-DAC, page 611-616. IEEE, (2008)