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Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time., , and . ISPD, page 166-173. ACM, (2003)A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique., , , and . VLSIC, page 236-. IEEE, (2015)Be Careful of Self and Mutual Inductance Formulae, and . (?)Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors., , , , and . ASP-DAC, page 593-599. IEEE, (2010)Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling., and . ASP-DAC, page 1168-1171. ACM Press, (2005)An efficient multi-touch tracking algorithm with a large number of points., , , , and . ICCE-Berlin, page 429-430. IEEE, (2014)Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (11): 1767-1771 (2012)Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup., , , and . DATE, page 1799-1802. IEEE, (2021)An optimal algorithm for sizing sequential circuits for industrial library based designs., , , , , and . ASP-DAC, page 148-151. IEEE, (2008)ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction., , and . DAC, page 163-166. ACM, (2005)