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Session 21 overview: Analog techniques: Analog subcommittee., and . ISSCC, page 356-357. IEEE, (2012)2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS., , , , , , , and . ISSCC, page 52-53. IEEE, (2014)High-speed transceivers: Standards, challenges, and future., , , , , and . ISSCC, page 522-523. IEEE, (2011)Technologies that could change the world - You decide!, and . ISSCC, page 515. IEEE, (2012)A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 48 (11): 2582-2594 (2013)Time-Variant Characterization and Compensation of Wideband Circuits., , , and . CICC, page 487-490. IEEE, (2007)Session 10 overview: Analog techniques., and . ISSCC, page 170-171. IEEE, (2013)F6: Mixed-signal/RF design and modeling in next-generation CMOS., , , and . ISSCC, page 510-511. IEEE, (2013)Clocking circuits for wireline communications., and . CICC, page 526-527. IEEE, (2005)Design of high-speed wireline transceivers for backplane communications in 28nm CMOS., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2012)