( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
NEM relay design with biconditional binary decision diagrams.

, , , и . NANOARCH, стр. 45-50. IEEE Computer Society, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Giovanni Federigo De Santi

Cristiano Micheli

Andrea Micheli

Karl Micheli

Walter Micheli

 

Другие публикации лиц с тем же именем

Power distribution paths in 3-D ICS., и . ACM Great Lakes Symposium on VLSI, стр. 263-268. ACM, (2009)A novel approach for network on chip emulation., , , , , , и . ISCAS (3), стр. 2365-2368. IEEE, (2005)Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing., , и . NanoNet, том 20 из Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, стр. 189-199. Springer, (2009)Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits., , и . CoRR, (2021)Three-Input Gates for Logic Synthesis., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)Emerging Technology-Based Design of Primitives for Hardware Security., , , , , , , , и . ACM J. Emerg. Technol. Comput. Syst., 13 (1): 3:1-3:19 (2016)Design and Automation for Quantum Computation and Quantum Technologies., , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (3): 581-583 (2022)Design for Testability of Gated-Clock FSMs., , и . ED&TC, стр. 589-597. IEEE Computer Society, (1996)Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks., , , , и . ED&TC, стр. 514-520. IEEE Computer Society, (1997)3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory., , , , и . VLSI-SoC, стр. 30-35. IEEE, (2012)