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Disambiguation of "Otero, Andrés"

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A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images.

, , , , , , and . Remote. Sens., 10 (11): 1790 (2018)

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Lourdes Otero León

Concepción Otero Moreno

Andrés Kecskeméthy

Andrés Bejas

Andrés Kling

 

Other publications of authors with the same name

A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems., , , , , , and . FPL, page 1-4. IEEE, (2014)Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics., , and . AHS, page 51-58. IEEE, (2018)A Framework for Fast Prototyping of Photo-realistic Environments with Multiple Pedestrians., , , , , and . ICRA, page 9083-9089. IEEE, (2023)Just-In-Time Composition of Reconfigurable Overlays (Invited Talk)., , , and . PARMA-DITAM@HiPEAC, volume 100 of OASIcs, page 2:1-2:13. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2022)A scalable evolvable hardware processing array., , , , and . ReConFig, page 1-7. IEEE, (2013)FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework., , , , , and . Sensors, 18 (6): 1877 (2018)A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution., , and . ARC, volume 13569 of Lecture Notes in Computer Science, page 47-61. Springer, (2022)Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads., , , and . Microprocess. Microsystems, (2024)A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays., , , , , and . IPDPS Workshops, page 182-191. IEEE, (2013)Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs., , , , , , and . FPL, page 369-375. IEEE Computer Society, (2011)