( en | de | ru )

 

Disambiguation of "de la Torre, Eduardo"

Author of the publication

copydeleteadd this publication to your clipboard
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems.

, , , , , , and . FPL, page 1-4. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Martino La Torre

Hector la Torre

Luis La Torre

Silvia Eunice Gutiérrez de la Torre Julius-Maximilians-Universität Würzburg

Eduardo La Riega

 

Other publications of authors with the same name

A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC., , , , , and . CPS Summer School, PhD Workshop, volume 2457 of CEUR Workshop Proceedings, page 107-118. CEUR-WS.org, (2019)Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support., , , , , and . AHS, page 184-191. IEEE, (2011)Automatic generation of identical routing pairs for FPGA implemented DPL logic., , , and . ReConFig, page 1-6. IEEE, (2012)Generic Systolic Array for Run-Time Scalable Cores., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 4-16. Springer, (2010)Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1057-1061. Springer, (2004)Message from the chairs., , , and . ReCoSoC, page 1. IEEE, (2015)A dynamic communication strategy for the distributed ATPG system DPLATON., , , and . EURO-DAC, page 271-276. IEEE Computer Society, (1993)Execution modeling in self-aware FPGA-based architectures for efficient resource management., , , , , and . ReCoSoC, page 1-8. IEEE, (2015)Accelerating the evolution of a systolic array-based evolvable hardware system., and . Microprocess. Microsystems, (2018)A digital system to emulate wireless networks., , , and . IET Comput. Digit. Tech., 1 (5): 444-450 (2007)