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Switch folding: network-on-chip routers with time-multiplexed output ports., , , и . DATE, стр. 344-349. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case., , , , , , и . ISCAS, стр. 1-5. IEEE, (2020)2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)., , , , , , и . DFT, стр. 1-4. IEEE, (2020)Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage., , , и . IVSW, стр. 61-66. IEEE, (2019)Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation., и . Hot Interconnects, стр. 67-74. IEEE Computer Society, (2008)Virtual-scan: a novel approach for software-based self-testing of microprocessors., , и . ISCAS (5), стр. 237-240. IEEE, (2003)ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3015-3028 (2015)Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching., , , и . Integr., (2021)IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications., , , , и . CoRR, (2023)LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride., , и . ISVLSI, стр. 200-205. IEEE, (2022)