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A Modified Rejection-Based Architecture to Find the First Two Minima in Min-Sum-Based LDPC Decoders., , , , and . WCNC, page 1-6. IEEE, (2020)Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS., , , , , , , , and . VTC Spring, page 1-5. IEEE, (2022)OFDM Transmission over a Short-Range 240 GHz Wireless Link: Performance Analysis., , , , , and . WSA, page 1-5. VDE Berlag / IEEE, (2021)Amplitude- and phase-modulated PSSS for wide bandwidth mixed analog-digital baseband processors in THz communication., , , , , , and . VTC2023-Spring, page 1-6. IEEE, (2023)Modulation and Coding Schemes for Variable-Rate Parallel Sequence Spread Spectrum., , , , , and . PIMRC, page 446-451. IEEE, (2021)1542 Gbps Fully Pipelined Fast-SSC Decoding of Polar Codes., , , and . PIMRC, page 1320-1325. IEEE, (2022)Towards 100 Gbps wireless communication: Investigation of FEC interleavers for PSSS-15 spreading., and . EUROCON, page 619-623. IEEE, (2017)Modular Data Link Layer Processing for THz communication., , , , and . DDECS, page 1-5. IEEE, (2019)Low power sensor node processor architecture., , , and . ICECS, page 914-917. IEEE, (2010)An Unnoticed Property in QC-LDPC Codes to Find the Message from the Codeword in Non-Systematic Codes., , , , and . EuCNC, page 6-9. IEEE, (2019)