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Disambiguation of "Flich, José"

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Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies.

, , , and . Euro-Par, volume 3648 of Lecture Notes in Computer Science, page 1024-1034. Springer, (2005)

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Humberto Jorge José

Nadine José Gonzalez

José Baena

José Teixeira

José Izquierdo

 

Other publications of authors with the same name

Silicon-aware distributed switch architecture for on-chip networks., , , , and . J. Syst. Archit., 59 (7): 505-515 (2013)Network-on-Chip virtualization in Chip-Multiprocessor Systems., , , and . J. Syst. Archit., 58 (3-4): 126-139 (2012)Fault-Tolerant Vertical Link Design for Effective 3D Stacking., , , , and . IEEE Comput. Archit. Lett., 10 (2): 41-44 (2011)Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms., , and . DATE, page 1-6. IEEE, (2023)Understanding cache hierarchy interactions with a program-driven simulator., , , and . WCAE, page 30-35. ACM, (2007)GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal., , , and . ISC Workshops, volume 13999 of Lecture Notes in Computer Science, page 593-604. Springer, (2023)Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration., , and . DATE, page 806-811. ACM, (2015)A fast centralized computation routing algorithm for self-configuring NoC systems., , , and . HiPC, page 1-10. IEEE Computer Society, (2011)Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip., , , and . NOCS, page 169-176. IEEE Computer Society, (2012)Yield-oriented evaluation methodology of network-on-chip routing implementations., , , , , , , , and . SoC, page 100-105. IEEE, (2009)