Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.

J. Segundo, L. Quintanilla, J. Álvarez, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Integr., 42 (1): 24-33 (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jesús Miguel Carnicer Álvarez

Julián Jesús Fernández Arias

Pedro Miguel d' Jesús Montilva

Rodrigo Álvarez

Jesús Araiza

Other publications of authors with the same name

Design of a switched opamp-based bandpass filter in a 0.35 μm CMOS technology.L. Quintanilla, J. Álvarez, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez, and A. Rueda. ICECS, page 29-32. IEEE, (2002)A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.J. Segundo, L. Quintanilla, J. Álvarez, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Integr., 42 (1): 24-33 (2009)Design of a CMOS fully differential switched-opamp for SC circuits at very low power supply voltages.J. Álvarez, L. Quintanilla, L. Enríquez, J. Vicente, J. Barbolla, D. Vázquez, and A. Rueda. ICECS, page 1545-1548. IEEE, (2001)Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator.L. Quintanilla, J. Álvarez, J. Segundo, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Microelectron. J., 42 (1): 148-157 (2011)Stable high-order delta-sigma digital-to-analog converters.P. Kiss, J. Álvarez, D. Li, and V. Boccuzzi. IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 200-205 (2004)Nonlinearity correction for multibit ΔΣ DACs.J. Álvarez, P. Kiss, V. Boccuzzi, L. Quintanilla, L. Enríquez, J. Vicente, D. Bisbal, J. Pablo, and J. Barbolla. IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (6): 1033-1041 (2005)Stable high-order delta-sigma DACS.P. Kiss, J. Álvarez, and D. Li. ISCAS (1), page 985-988. IEEE, (2003)Effect of Finite amplifier Bandwidth and excess Loop Delay in a Parallel CT δς ADC for OFDM UWB receivers.L. Quintanilla, J. Álvarez, J. Segundo, L. Enríquez, J. Hernández-Mangas, and J. Vicente. J. Circuits Syst. Comput., (2013)A 1.2 V, 130 nm CMOS parallel continuous-time ΣΔ ADC for OFDM UWB receivers.J. Segundo, J. Álvarez, L. Quintanilla, L. Enríquez, J. Hernández-Mangas, and J. Vicente. Microelectron. J., 43 (4): 288-297 (2012)A parallel, CT-ΔΣ based ADC for OFDM UWB receivers in 130 nm CMOS.J. Segundo, J. Álvarez, L. Quintanilla, L. Enríquez, J. Hernández-Mangas, and J. Vicente. ICECS, page 406-409. IEEE, (2011)

BibSonomy

Disambiguation of "Álvarez, Jesús Arias"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.

Please choose a person to relate this publication to

Jesús Miguel Carnicer Álvarez

Julián Jesús Fernández Arias

Pedro Miguel d' Jesús Montilva

Rodrigo Álvarez

Jesús Araiza

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Álvarez, Jesús Arias"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.

Please choose a person to relate this publication to

Jesús Miguel Carnicer Álvarez

Julián Jesús Fernández Arias

Pedro Miguel d' Jesús Montilva

Rodrigo Álvarez

Jesús Araiza

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter.