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Disambiguation of "Jain, Pulkit"

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Enhancing beneficial jitter using phase-shifted clock distribution.

, , , and . ISLPED, page 21-26. ACM, (2008)

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Pulkit Grover

Gora Jain

Arpit Jain

Himalaya Jain

Prabhat Jain

 

Other publications of authors with the same name

A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V., , , , , , , , , and 7 other author(s). ISSCC, page 212-214. IEEE, (2019)A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies., , , and . ISSCC, page 506-507. IEEE, (2011)The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (2): 280-291 (2015)Logic-compatible embedded DRAM design for memory intensive low power systems., , and . ISCAS, page 277-280. IEEE, (2010)A multi-story power delivery technique for 3D integrated circuits., , , and . ISLPED, page 57-62. ACM, (2008)A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM., , and . ISLPED, page 119-120. ACM, (2009)A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique., , , , , , , , , and 11 other author(s). ISSCC, page 214-216. IEEE, (2019)A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor., , , and . IEEE J. Solid State Circuits, 47 (10): 2517-2526 (2012)Enhancing beneficial jitter using phase-shifted clock distribution., , , and . ISLPED, page 21-26. ACM, (2008)An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs., , and . ESSDERC, page 262-265. IEEE, (2012)