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Fitting Generalized Additive Models with the GAM Procedure. стр. Paper 256-26. (2001)Anàlisi de dades; GAM; Smoothing; SAS.Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)TM: a new and simple topology for interconnection networks., , и . J. Supercomput., 66 (1): 514-538 (2013)Handling the pin overhead problem of DFTs for high-quality and at-speed tests., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1105-1113 (2002)Cooperative power scheduling for a network of MIMO links., , и . IEEE Trans. Wirel. Commun., 9 (3): 939-944 (2010)Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing., , и . VTS, стр. 1-6. IEEE, (2020)Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , и . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)A power-effective scan architecture using scan flip-flops clustering and post-generation filling., , и . ACM Great Lakes Symposium on VLSI, стр. 517-522. ACM, (2009)Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture., , , , и . ATS, стр. 299-306. IEEE, (2006)NetBouncer: Active Device and Link Failure Localization in Data Center Networks., , , , , , , и . NSDI, стр. 599-614. USENIX Association, (2019)