( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
The Effect of Wire Length Minimization on Yield.

, , и . DFT, стр. 97-105. IEEE Computer Society, (1994)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Hillel Koren

Christoph Korenke

Sergey Koren

Viktoria Koren

Aleksej Korenkov

 

Другие публикации лиц с тем же именем

Identification of in-field defect development in digital image sensors., , , , , и . Digital Photography, том 6502 из SPIE Proceedings, стр. 65020Y. SPIE, (2007)Using Simulated Annealing for Mapping Algorithms onto Data Driven Arrays., и . ICPP (1), стр. 123-127. CRC Press, (1991)Incorporating Yield Enhancement into the Floorplanning Process., и . IEEE Trans. Computers, 49 (6): 532-541 (2000)Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems., и . IEEE Trans. Computers, 40 (9): 1024-1033 (1991)Countermeasures against fault attacks on software implemented AES: effectiveness and cost., , , , и . WESS, стр. 7. ACM, (2010)Countermeasures against Branch Target Buffer Attacks., , , и . FDTC, стр. 75-79. IEEE Computer Society, (2007)Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-threshold Devices through an Example of a 65nm AES Implementation., , , , , и . RFIDSec, том 7055 из Lecture Notes in Computer Science, стр. 48-60. Springer, (2011)Effective analytical delay model for transistor sizing., и . ASP-DAC, стр. 387-392. ACM Press, (2005)Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard., , , , и . IEEE Trans. Computers, 52 (4): 492-505 (2003)An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors., , и . PACT, стр. 219. IEEE Computer Society, (2011)