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"Timing closure by design, " a high frequency microprocessor design methodology.

S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong, B. Flachs, H. Hofstee, N. Kojima, O. Kwon, K. Lee, D. Meltzer, K. Nowka, J. Park, J. Peter, J. Silberman, O. Takahashi, and P. Villarrubia. DAC, page 712-717. ACM, (2000)

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Sang-H Sin

Bernd Sang

Sibylle Sang

Jürgen Sang

H -H Kaatz

Other publications of authors with the same name

A low-noise TTL-compatible CMOS off-chip driver circuit.S. Dhong, M. Tanaka, S. Tomashot, and T. Kirihata. IBM J. Res. Dev., 39 (1-2): 105-112 (1995)Prospective for nanowire transistors.J. Colinge, and S. Dhong. CICC, page 1-8. IEEE, (2013)A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB.M. Kuo, O. Takahashi, P. Yang, C. Lin, M. Wang, P. Wang, and S. Dhong. CICC, page 1-4. IEEE, (2013)Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology.H. Hsieh, S. Dhong, C. Lin, M. Kuo, K. Tseng, P. Yang, K. Huang, M. Wang, and W. Hwang. CICC, page 1-3. IEEE, (2015)Cell Broadband Engine Processor Design Methodology.O. Takahashi, E. Behnen, S. Cottier, P. Coulman, S. Dhong, B. Flachs, H. Hofstee, C. Johnson, and S. Posluszny. CICC, page 711-716. IEEE, (2007)A 64Kb - 32 DRAM for graphics applications.T. Sunaga, K. Hosokawa, S. Dhong, and K. Kitamura. IBM J. Res. Dev., 39 (1-2): 43-50 (1995)"Timing closure by design, " a high frequency microprocessor design methodology.S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong, B. Flachs, H. Hofstee, N. Kojima, O. Kwon, K. Lee and 7 other author(s). DAC, page 712-717. ACM, (2000)Design methodology for a 1.0 GHz microprocessor.S. Posluszny, N. Aoki, D. Boerstler, J. Burns, S. Dhong, U. Ghoshal, H. Hofstee, D. LaPotin, K. Lee, D. Meltzer and 5 other author(s). ICCD, page 17-23. IEEE Computer Society, (1998)The circuit design of the synergistic processor element of a CELL processor.O. Takahashi, R. Cook, S. Cottier, S. Dhong, B. Flachs, K. Hirairi, A. Kawasumi, H. Murakami, H. Noro, H. Oh and 3 other author(s). ICCAD, page 111-117. IEEE Computer Society, (2005)A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.S. Dhong, R. Guo, M. Kuo, P. Yang, C. Lin, K. Huang, M. Wang, and W. Hwang. CICC, page 1-4. IEEE, (2014)

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Disambiguation of "Dhong, Sang H."

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"Timing closure by design, " a high frequency microprocessor design methodology.

Please choose a person to relate this publication to

Sang-H Sin

Bernd Sang

Sibylle Sang

Jürgen Sang

H -H Kaatz

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Dhong, Sang H."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML "Timing closure by design, " a high frequency microprocessor design methodology.

Please choose a person to relate this publication to

Sang-H Sin

Bernd Sang

Sibylle Sang

Jürgen Sang

H -H Kaatz

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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"Timing closure by design, " a high frequency microprocessor design methodology.