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Другие публикации лиц с тем же именем

Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability., , и . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 580-584 (2013)WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements., , и . VLSI Design, стр. 479-484. IEEE Computer Society, (2009)Combating Aging with the Colt Duty Cycle Equalizer., , , и . MICRO, стр. 103-114. IEEE Computer Society, (2010)False Path Aware Timing Yield Estimation under Variability., , , и . VTS, стр. 161-166. IEEE Computer Society, (2009)AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors., и . ASP-DAC, стр. 725-730. IEEE, (2011)Improving platform energy: chip area trade-off in near-threshold computing environment., , и . ICCAD, стр. 318-325. IEEE, (2013)Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating., , , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (10): 1885-1890 (2012)Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits., и . ISQED, стр. 791-796. IEEE, (2010)Cost-effective power delivery to support per-core voltage domains for power-constrained processors., , , и . DAC, стр. 56-61. ACM, (2012)Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors., и . ISLPED, стр. 189-194. ACM, (2009)