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Disambiguation of "Yoshida, Takeshi"

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A 76-Gbit/s 265-GHz CMOS Receiver.

, , , , , , , , , , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Takeshi Morita

Takuro Yoshida

Daisuke Yoshida

Takeshi Morita

Takeshi Imamura

 

Other publications of authors with the same name

A 1V supply successive approximation ADC with rail-to-rail input voltage range., , , and . ISCAS (1), page 192-195. IEEE, (2005)A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface., , , , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 2988-2998 (2022)Multi-Scale Feature Aggregation Based Multiple Instance Learning for Pathological Image Classification., , , , and . ICPRAM, page 619-628. SCITEPRESS, (2023)254-GHz-to-299-GHz Down Conversion Mixer Using 45nm SOI CMOS., , , , , and . MWSCAS, page 1-4. IEEE, (2022)Semi-Hard Margin Support Vector Machines for Personal Authentication with an Aerial Signature Motion., and . ICANN (4), volume 12894 of Lecture Notes in Computer Science, page 333-344. Springer, (2021)Spatial and temporal segmented dense trajectories for gesture recognition., , , , and . QCAV, volume 10338 of SPIE Proceedings, page 103380F. SPIE, (2017)124-GHz CMOS quadrature voltage-controlled oscillator with fundamental injection locking., , , , and . A-SSCC, page 1-4. IEEE, (2015)Development of an implantable wireless ECoG 128ch recording device for clinical brain machine interface., , , , , , , , , and . EMBC, page 1867-1870. IEEE, (2013)A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique., , , , and . IEICE Trans. Electron., 89-C (6): 769-774 (2006)A Neural Signal Detection Amplifier with Low-frequency Noise Suppression., , , , , and . ISCAS, page 661-664. IEEE, (2009)