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Disambiguation of "Nair, Sarath Mohanachandran"

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Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.

, , , , , , , and . IRPS, page 1-6. IEEE, (2019)

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Chithra Kumaran Nair

Photodisintegration studies of astrophysically relevant p-nuclei. TU Dresden, (2009)

Ramya Nair

Banafsheh Nairizi

Jayan Nandanan Nair

Suraj Nair

 

Other publications of authors with the same name

Variation-aware Fault Modeling and Test Generation for STT-MRAM., , , , and . IOLTS, page 80-83. IEEE, (2019)Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects., , , , , , , and . IRPS, page 1-5. IEEE, (2020)Dynamic Faults based Hardware Trojan Design in STT-MRAM., , , and . DATE, page 933-938. IEEE, (2020)Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory., , and . ETS, page 1-6. IEEE, (2020)Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis., , , , , , , , and . VTS, page 1-10. IEEE, (2020)Mitigating Read Failures in STT-MRAM., , and . VTS, page 1-6. IEEE, (2020)Variation Analysis, Fault Modeling and Yield Improvement of Emerging Spintronic Memories. Karlsruhe University, Germany, (2020)base-search.net (ftubkarlsruhe:oai:EVASTAR-Karlsruhe.de:1000119696).Using multifunctional standardized stack as universal spintronic technology for IoT., , , , , , , , , and 8 other author(s). DATE, page 931-936. IEEE, (2018)VAET-STT: A variation aware estimator tool for STT-MRAM based memories., , , , and . DATE, page 1456-1461. IEEE, (2017)A Universal Spintronic Technology based on Multifunctional Standardized Stack., , , , , , , , and . DATE, page 394-399. IEEE, (2020)