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A Loop Optimization Method for Dataflow Architecture.

, , , , , , , and . HPCC/DSS/SmartCity/DependSys, page 202-211. IEEE, (2022)

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Circuit implementation of floating point range reduction for trigonometric functions., , , , , and . ISCAS, page 3010-3013. IEEE, (2007)Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors., , and . CIT (1), page 86-91. IEEE Computer Society, (2009)Streamline Ring ORAM Accesses through Spatial and Temporal Optimization., , , , , , and . HPCA, page 14-25. IEEE, (2021)Simple and Efficient Heterogeneous Graph Neural Network., , , , and . AAAI, page 10816-10824. AAAI Press, (2023)Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture., , , , and . DAC, page 115. ACM, (2019)On the properties of data migration based on topology pattern keeping on cache hierarchy., , , , and . IGSC, page 1-4. IEEE Computer Society, (2016)Preliminary Investigation of Accelerating Molecular Dynamics Simulation on Godson-T Many-Core Processor., , , , , , and . Euro-Par Workshops, volume 6586 of Lecture Notes in Computer Science, page 349-356. Springer, (2010)Instruction Vulnerability Test and Code Optimization Against DVFS Attack., , , , , , , and . ITC-Asia, page 49-54. IEEE, (2019)Simplified Multi-Ported Cache in High Performance Processor., and . IEEE NAS, page 9-14. IEEE Computer Society, (2007)High Performance Matrix Multiplication on Many Cores., , , , and . Euro-Par, volume 5704 of Lecture Notes in Computer Science, page 948-959. Springer, (2009)