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18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.

, , , , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 318-319. IEEE, (2016)

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Jae-Ho Choi

Jae Hyeong Choi

Jae-Ou Choi

Jae-Young Song

Jae-Young Song

 

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