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A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme., , , , , , , , , и 25 other автор(ы). ISSCC, стр. 380-382. IEEE, (2019)A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface., , , , , , , , , и 6 other автор(ы). ISCAS, стр. 3861-3864. IEEE, (2010)Design considerations of HBM stacked DRAM and the memory architecture extension., , , , , , и . CICC, стр. 1-8. IEEE, (2015)Group Dancing Mobile Flower Robots with Moving Mechanism, Mobility and Localization Functions., , , , и . ISR/ROBOTIK, стр. 1-6. VDE Verlag, (2010)18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface., , , , , , , , , и 12 other автор(ы). ISSCC, стр. 318-319. IEEE, (2016)High bandwidth memory(HBM) with TSV technique., , , , , , , , , и 9 other автор(ы). ISOCC, стр. 181-182. IEEE, (2016)25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 432-433. IEEE, (2014)