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RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis.

, and . ISVLSI, page 266-267. IEEE Computer Society, (2005)

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Logic Reduction in Timed Asynchronous Circuits., and . ISCAS, page 1223-1226. IEEE, (1995)A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks., and . DATE, page 721-728. IEEE Computer Society, (1998)Dynamically Reconfigurable Hardware for Object-Oriented Processing., and . PARELEC, page 181-186. IEEE Computer Society, (2004)TinyTPM: A lightweight module aimed to IP protection and trusted embedded platforms., , , and . HOST, page 6-11. IEEE Computer Society, (2011)VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip., , and . ASYNC, page 188-. IEEE Computer Society, (2000)RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis., and . ISVLSI, page 266-267. IEEE Computer Society, (2005)An Efficient Approach to Anonymous Distribution of ITS Messages in Geographic Areas via LTE and IRS Networks., and . ICISSP (Revised Selected Papers), volume 691 of Communications in Computer and Information Science, page 192-214. Springer, (2016)dcTPM: A Generic Architecture for Dynamic Context Management., , , and . ReConFig, page 211-216. IEEE Computer Society, (2011)Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT., , and . ASYNC, page 219-. IEEE Computer Society, (1999)Audio watermarking algorithm for real-time speech integrity and authentication., and . MM&Sec, page 220-226. ACM, (2004)