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MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures.

, , , and . IEICE Electron. Express, 9 (17): 1414-1422 (2012)

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A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs., , , , and . APCCAS, page 244-247. IEEE, (2014)Energy-efficient High-level Synthesis for HDR Architectures., , and . Inf. Media Technol., 7 (4): 1319-1330 (2012)An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures., , and . ISCAS, page 576-579. IEEE, (2012)Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling., , , and . Inf. Media Technol., 8 (4): 913-923 (2013)Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating., , , and . Inf. Media Technol., 10 (1): 1-7 (2015)MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures., , , and . IEICE Electron. Express, 9 (17): 1414-1422 (2012)An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2014)